Dynamic random access memory chips (DRAMs) are the most commonly used memory components. A DRAM exhibits a regular but complex structure and consists of millions of transistors and storage capacitors that enable a wide variety of memory module errors. Those types can be grouped into four categories:
1. Stuck-at faults which occur when the logical value of a memory cell is always 0 or 1 and can't be changed. PA1 2. Transition faults which prevent a cell from undergoing a 1 to 0 or 0 to 1 transition. PA1 3. Coupling faults which occur when a transition in one cell changes the memory value in another cell. PA1 4. Address decoder faults which access multiple cells with one address, never access some addresses, or address one cell with multiple addresses.
Many systems have been developed to test for various memory cell fault conditions. U.S. Pat. No. 5,274,648 to Eikill et al. describes a memory card which includes resident registers for retaining a data pattern stored to a memory array on the card; for storing a value read out from a memory position for comparison purposes, and logic circuitry for performing the comparison. Error indications are provided to a processor in the event that the register contents are not the same.
U.S. Pat. No. 4,342,084 to Sager et al. provides a method for performing tests on memory modules which enables a set of modules to be "fenced" while the remainder of the system operates with "unfenced" modules. The memory modules within the fenced area are then subjected to a test protocol which increments line addresses, while sequentially comparing true and complement patterns. U.S. Pat. No. 4,262,668 to Dancker et al. describes apparatus for testing a card mounted microprocessor/DRAM circuit. The Dancker et al. system employs two different clock generators, one of which makes the DRAM appear to the tester as a static memory device.
The following U.S. Pat. Nos. provide further descriptions of test circuits and techniques for memory modules: 4,969,148 to Nadeau-Dostie et al.; 4,379,259 to Varadi et al; 4,942,576 to Busack et al.; and 5,073,891 to Patel. The following references are of a more general nature and describe various techniques and systems for testing of semiconductor memories: "Design and Application of Semiconductor Memory Test Hardware", Shaw, GTE Automatic Electric Technical Journal, April, 1976, pages 65-79; "Design Aids and Hardware Testing of Microprocessor System Circuit Packs", Grason IEEE Proc. of Symposium on Design Automation & Microprocessor, Feb. 24, 1997, pages 95-99; "A Novel Built-In Self-Repair Approach to VLSI Memory Yield Enhancement", Mazumder et al., 1990 International Test Conference, paper 36.3, pages 833-841; "Chip Level Test Improvements Using Cross Check Gate-Array Devices", Fertsch, Electro-92 Conference Record, pages 266-270 (1992); and "Hardware Algorithm for Static and Dynamic RAMs Testing" Salem et al., Modeling, Simulation and Control, A, AMSE Press, Vol. 40, No. 1, 1991, pages 57-63.
Various algorithms have been derived to enable functional testing of DRAM modules. Those algorithms write specific patterns to a DRAM array and then check the read data for accuracy. In general, the test times of the algorithms increase with the size of the memory, linearly at best and as the square of the number of accesses to the memory chip at worst. Ruedy et al. describe an application of the "March" algorithm. That algorithm writes different values, sequentially, to individual bit positions in a memory and tests the output values to assure functionality of each bit position. The March algorithm detects faults by performing multiple reads and writes of patterns. In order to insure that the memory is defect free, the March algorithm pattern must be run against every bit position in the array. Performing this task using software requires an extended period of time because of the requirement to set hardware pointers/registers and to implement received commands. More specifically, the processor must write the pattern, read the pattern and compare it to the original pattern. Thus, if a processor takes three clock cycles per instruction, it takes three cycles to write the pattern, three cycles to read the pattern, and three cycles to compare the read data with the pattern in order to provide error indications. Thus, a total of nine processor cycles is required which must then be multiplied by the number of bit positions to arrive at the total number of cycle times required for the memory test. For large DRAM arrays, the required time becomes so long as to make the March algorithm unusable.
Accordingly, it is an object of this invention to provide an improved memory test procedure and system which reduces the amount of time required to test a large memory array.
It is another object of this invention to provide an improved memory test system and procedure which takes advantage of alternative addressing procedures that are available for commercially available memory modules.
It is still another object of this invention to provide an improved memory test system which automatically enables insertion of spare memory modules upon a finding of an uncorrectable error in a primary memory module.